Description: 按键扫描 51单片机加8279
8279通过74LS 138译码器扩展4×4键盘、6位显示器。
由3-8译码器对SL0～SL2译出键扫描线，由另一3-8译码器译出显示器的位扫描线，并采用了编码扫描方式。
为了防止出现重键现象，扫描输出线高位SL3不参加键扫描译码。CPU对8279的监视采用了查询方式，故8279的中断请求信号IRQ悬空未用。
-Scan button 82,798,279 plus 51 single-chip decoder 74LS 138 through the expansion of 4 × 4 keyboard, the display 6. From 3-8 decoder SL0 ~ SL2 translated to the key scanning line, by another 3-8 decoder translated display scan line, and uses code scanning. In order to prevent the emergence of the phenomenon of re-key, scan the output line does not take part in high level SL3 scan decoding keys. CPU on the 8279 surveillance using the query mode, the 8279 interrupt request signal IRQ left unused. Platform: |
Size: 2048 |
Author:qiumh |
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Description: 3對8解碼器
可提供3線8選擇之功能
可輕易改成4選16-Three pairs of 8 decoder may choose to provide 3-line 8 of function can be easily changed to 4 election 16 Platform: |
Size: 1024 |
Author:jiayi |
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Description: 这是一用VHDL语言描述的8线-3线译码器,希望对大家有用-This is a description using VHDL, 8-line-3 line decoder, we want to be useful Platform: |
Size: 79872 |
Author:万勇 |
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Description: 这是一用VHDL语言描述的3线-8线译码器,希望对大家有用-This is a description using VHDL, 3-wire-8 line decoder, we want to be useful Platform: |
Size: 299008 |
Author:万勇 |
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Description: 16×16LED点阵显示
描述：74LS138是3-8译码器，两块74LS138组成4-16译码器，在工作的某一时刻，4-16译码器只输出一个有效电平来驱动一行点阵显示。
-16 × 16LED dot matrix display Description: 74LS138 decoder is 3-8, 4-16 composed of two 74LS138 decoder, a time at work, 4-16 decoder outputs only an effective level to drive the line dot matrix display. Platform: |
Size: 11264 |
Author:quyinlong |
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Description: 利用Active-VHDL 来仿真测试74LS138 译码器，74LS138 译码器是3 线-8 线译
码器。-To the use of Active-VHDL simulation test 74LS138 decoder, 74LS138 decoder is a 3-wire-8 line decoder. Platform: |
Size: 11264 |
Author:stronger |
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Description: 3/8译码器
译码输入：A、B、C，输入信号：EN；EN输入信号正常时为高电平，当EN为低电平时，无论A、B、C输入信号为何值，输出Y0…Y7均为高电平“1”。
电路逻辑功能实现后，可将该逻辑功能下载到FPGA中。注意选择：输入信号线4根、输出线8根（接发光二极管指示灯）；测试时根据输入信号的变化观察输出信号的改变。-3/8 decoder decodes input: A, B, and C, the input signal: EN en normal input signal is high, when EN is low, whether A, B, C why the input signal value, the output Y0 ... Y7 are high " 1." Circuit logic functions, the logic functions to be downloaded to the FPGA. Note options: the input signal line 4, the output line 8 (connected to the light emitting diodes LEDs) when tested according to the changes in the input signal to observe the output signal changes. Platform: |
Size: 39936 |
Author:文鸿捷 |
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Description: 用Verilog HDL设计3线-8线译码器，ena是译码器的使能控制端，当ena=1时译码器工作，ena=0时译码器被禁止，8个输出均为高电平
用Verilog HDL设计具有三态输出的8D锁存器。-3-to-8 line decoder, ENA is designed using Verilog HDL the decoder enable control terminal, when ena = 1 time decoder, ENA = 0 time decoder is disabled, 8 outputs are high 8D latch with tri-state output level using Verilog HDL design. Platform: |
Size: 1024 |
Author:赵玉著 |
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Description: 数字电路中常用的3线-8线译码器及8线-3线优先编码器的VHDL语言的功能描述-That is commonly used in digital circuit lines to 3-8 8 line to 3 line priority encoder decoder and the function of the VHDL language description Platform: |
Size: 3072 |
Author:王宝 |
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Description: 基于FPGA的138译码器的实现，可以实现对应的3线8线译码器的功能，适合初学者使用。-138 decoder based on FPGA implementation can be achieved corresponding 3 line 8 line decoder function, suitable for beginners to use. Platform: |
Size: 576512 |
Author:黄兴 |
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Description: 译码电路设计，用VHDL语言设计一个3线-8线译码器的方法-Decoding circuit design using VHDL language to design a 3-to-8 line decoder method Platform: |
Size: 1024 |
Author:赵丽丽 |
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Search - 3 line to 8 line decoder